逻辑电路设计基础

第1章   导论                  
 11数制的简单回顾                  
 111 八进制数和十六进制数                  
 112 二进制加法                  
 113 有符号数                  
 114 二进制减法                  
 115 二十进制码（BCD）                  
 12 组合系统的设计过程                  
 13 列真值表                  
 14 无关条件                  
 15 实验室                  
 16 解题实例                   
                   
  第2章 开关代数和逻辑电路                   
 21 开关代数的定义                  
 22 开关代数的基本性质                  
 23 代数函数的处理                  
 24 用与门. 或门和非门实现逻辑函数                  
 25 从真值表到代数表达式                   
 26 卡诺图初步                  
 27 补和或与                  
 28 与非门. 或非门和异或门                  
 29 代数表达式的化简                  
 210 代数函数的处理及其与非门实现                  
 211 布尔代数                  
 212 解题实例                  
 213 习题                   
                   
                   
                   
  第3章 两种规范性的化简方法                   
 3.1  卡诺图                  
  3.1.1 用卡诺图求解最简与或表达式                  
  3.1.2 无关项                  
  3.1.3 或与式                  
  3.1.4 最省门的电路实现                  
  3.1.5 五变量和六变量的卡诺图                  
  3.1.6 多输出问题                  
 3.2  规律性的最简化方法                  
 3.2.1 单输出的迭代合意                  
 3.2.2 单输出的质蕴含项表                  
 3.2.3 多输出问题的迭代合意                  
 3.3 解题实例                  
 3.4 习题                   
                   
 第4章 较大规模的系统设计                   
                   
 4.1 组合逻辑电路中的延时                  
 4.2 加法器                  
 4.3 译码器                  
 4.4 编码器和优先权编码器                  
 4.5 数据选择器                  
 4.6 三态门                  
 4.7  门阵列--ROM, PLA和PAL                  
 4.7.1 用只读存储器进行设计                  
 4.7.2 用可编程逻辑阵列进行设计                  
 4.7.3 用可编程阵列逻辑进行设计                  
 4.8  较大规模电路的例子                  
 4.8.1 七段显示                  
 4.8.2 差错编码和解码系统                  
 4.9 解题实例                  
 4.10 习题                   
  第5章 时序系统                   
 5.1 闩锁和触发器                   
 5.2 同步时序系统的设计过程                  
 5.3 时序系统的分析                  
 5.4 触发器的设计方法                  
 5.5 同步计数器的设计                  
 5.6 异步计数器的设计                  
 5.7 生成状态表和状态图                  
 5.8 解题实例                  
 5.9 习题                   
                   
  第6章 求解较大规模的时序问题                   
 6.1 移位寄存器                  
 6.2 计数器                  
 6.3 可编程逻辑器件（PLD）                  
 6.4 用ASM图进行设计                  
 6.5 硬件设计语言（HDL）                  
 6.6 更复杂的例子                  
 6.7 解题实例                  
 6.8 习题                   
                   
  第7章 时序电路化简                   
 7.1 列表法进行状态化简                  
 7.2  分割法                  
 7.2.1 分割的性质                  
 7.2.2 求SP分割                  
 7.3 用分割法进行状态化简                  
 7.4 选择状态分配                  
 7.5 解题实例                  
 7.6 习题                   
  附录A 实验