Chapter 1: Introduction
l.1 A Historical Perspective
1.2 Issues in Digital Integrated Circuit Design
l.3 To Pr()be Further
1.4 Exercises
PART l: A CIRCUIT PERSPECTIVE
Chapter 2: The Devices
2.l Introduction
2.2 The Diode
2.2.1 A First Glance at the Device
2.2.2 Static Behavior
2.2.3 Dynamic. or Transient, Behavior
2.2.4 The Actual Diode-Secondary Effects
2.2.5 The SPICE Diode Model
2.3 The MOS(FET) Transistor
2.3.l A First G1ance at the Device
2.3.2 Static Behavior
2.3.3 Dylla111ic Behavior
2.3.4 The Actual MOS Transistor-Secondary Effects
2.3.5 SPICE Models f()r the MOS Transistor
2.4 The Bipolar Transistor
2.4.l A First Glance at the Device
2.4.2 Static Behavior
2.4.3 Dynamic Behavior
2.4.4 The Actual Bipolar Transistor--Secondary Effects
2.4.5 SPICE Models for the Bipolar Transistor
2.5 A Word on Process Variations
2.6 Perspective f Future Device Deve1opments
2.7 Summary
2.8 TO Probe Further
2.9 Exercises and Design Problems
Appendix A: Layout Design Rules
Appendix B: Small-Signal Models
Chapter 3: The Inverter
3.1 Introduction
3.2 Definitions and Properties
3.2.1 Area and Complexity
3.2.2 Functionality and Robustness: The Static Behavior
3.2.3 Performance: The Dynamic Behavior
3.2.4 Power and Energy Consumption
3.3 The Static CMOS Inverter
3.3.l A First Glance
3.3.2 Eva1uating the Robustness of the CMOS Inverter: The Static Behavior
3.3.3 Performance of CMOS Inverter The Dynamic Behavior
3.3,4 Power Consumption and Power-De1ay Product
3.3.5 A Look into the Future: Effects of Technology Scaling
3.4 The Bipolar ECL Inverter
3.4.1 Issues in Bipolar Digital Design f A Case Study
3.4.2 The Emitter-Coupled Logic (ECL) Gate at a Glance
3.4.3 Robustness and Noise Immunity f The Steady-State Characteristics
3.4.4 ECL Switching Speed : The Transient Behavior
3.4.5 Power Consumption
3.4.6 Looking Ahead: Scaling the Technology
3.5 Perspective: Area, Performance, and Dissipation
3.6 Summary
3.7 TO Probe Further
3.8 Exercises and Design Problems
Chapter 4: Designing Combinational Logic Cates in CMOS
4.l Introduction
4.2 Static CMOS Design
4.2.1 Complementary CMOS
4.2.2 Ratioed Logic
4.2.3 Pass--Transistor Logic
4.3 Dynamic CMOS Design
4.3. l Dynamic Logic f Basic Principles
4.3.2 Performance of Dynamic Logic
4.3.3 Noise Considerations in Dynamic Design
4.3.4 Cascading Dynamic Gates
4.4 Power Consumption in CMOS Gates
4.4.l Switching Activity of a Logic Gate
4.4.2 Glitching in Static CMOS Circuits
4.4.3 Short-Circuit Currents in Static CMOS Circuits
4.4 4 Ana1yzing Power Consumption Using SPICE
4.4.5 Low-Power CMOS Design
4.5 Perspective: How to Choose a Logic Style
4.6 Summary
4.7 TO Probe Further
4.8 Exercises and Design Problems
Appendix C: Layout Techniques for Complex Cates
Chapter S: V6ry High Performance Digital Circuits
5.1 Introduction
5.2 Bipolar Gate Design
5.2.l Logic Design in ECL
5.2.2 Differential ECL
5.2.3 Current Mode Logic
5.2.4 ECL with Active Pull-Downs
5.2.5 Alternative Bipolar Logic Styles
5.3 The BiCMOS Approacl1
5.3.l The BiCMOS Gate at a Glance
5.3.2 The Static Behavior and Robustness Issues
5.3.3 Performance of the BiCMOS Inverter
5.3.4 Power Consumption
5.3.5 Techno1ogy Scaling
5.3.6 Designing BiCMOS Digital Gates
5.4 Digital Gallium Arsenide Design *
5.4.l GaAs Devices and Their Properties
5.4.2 GaAs Digital Circuit Design
5.5 Low--Temperature Digital Circuits *
5.5.l Low-Temperature Silicon Digital Circuits
5.5.2 Superconducting Logic Circuits
5.6 Perspective When to Use High--Performance Technologies
5.7 Summary
5.8 To Probe Further
5.9 Exercises and Design Problems
Appendix D: The Schottky-Barrier Diode
Chapter 6: Designing Sequential Logic Circuits
6.l Introduction
6.2 Static Sequential Circuits
6.2.l Bistability
6.2.2 Flip-Flop Classification
6.2.3 Master-Slave and Edge-Triggered FFs
6.2.4 CMOS Static Flip--Flops
6.2.5 Bipolar Static Flip-Flops
6.3 Dynamic Sequential Circuits
6.3.l The Pseudostatic Latch
6.3.2 The Dynamic Two-Phase Flip--Flop
6.3.3 The C2MOS Latch
6.3.4 NORA-CMOS-A Logic Sty1e for Pipelined Structures
6.3.5 True Sing1e-Phase Clocked Logic (TSPCL)
6.4 Non-Bistable Sequential Circuits
6 4.1 The Schmit1 Trigger
6.4.2 Monostable Sequential Circuits
6.4.3 Astable Circuits
6.5 Perspective: Choosing a Clocking Strategy
6.6 Summary
6.7 To Probe Further
6.8 Exercises and Design Problems
PART Il: A SYSTEMS PERSPECTIVE
Chapter 7: Designing Arithmetic Building Blocks
7.l Introduction
7.2 Datapaths in Digital Processor Architectures
7.3 The Adder
7.3.l The Binary Adder f Definitions
7.3.2 The Ful1 Adder: Circuit Design Considerations
7.3.3 The Binary Adder f Logic Design Considerations
7.4 The Multiplier
7.4.l The Multiplier' Definitions
7.4.2 The Array Multiplier
7.4.3 Other Multiplier Structures
7.5 The Shifter
7.5.l Barrel Shifter
7.5.2 Logarithmic Shifter
7.6 Other Arithmetic Operators
7.7 Power Considerations in Datapath Structures
7.7.l Reducing the Supply Voltage
7.7.2 Reducing the Effective Capacitance
7.8 Perspective f Design as a Trade-of T
7.9 Summary
7.l0 TO Probe Further
7.ll Exercises and Design Problems
Appendix E: From Datapath Schematics to Layout
Chapter 8: Coping with Interconnect
8.l Introduction
8.2 Capacitive Parasitics
8.2.l Modeling Interconnect Capacitance
8.2.2 Capacitance and Reliabi1ityXross Talk
8.2.3 Capacitance and Performance in CMOS
8.2.4 Capacitance and Performance in Bipolar Design
8.3 Resistive Parasitics
8.3.1 Modeling and Scaling of Interconnect Resistance
8.3.2 Resistance and Reliability-Ohmic Voltage Drop
8.3.3 Electromigration
8.3.4 Resistance and Per1orlTjance--RC Delay
8.4 Inductive Parasitics
8.4.1 Sources of Parasitic Inductances
8.4.2 Inductance and Reliability -Voltage Drop
8.4.3 Inductance and Performance--Transmission Line l
8.5 Comments on Packaging Technology
8.5.l Package Materials
8.5.2 Interconnect Levels
8.5.3 Thermal Considerations in Packaging
8.6 Perspective f When to Consider Interconnect Parasitics
8.7 Chapter Summary
8.8 To Probe Further
8.9 Exercises and Design Problems
Chapter 9: Timing issues in Digital Circuits
9.l Introduction
9.2 Clock Skew and Sequential Circuit Performance
9.2.l Single--Phase Edge-Triggered Clocking
9.2.2 Two--Phase Master-Slave Clocking
9.2.3 Other Clocking Styles
9.2.4 How to Counter Clock Skew Problems
9.2.5 Case Study--The Digital Alpha 2 I l64 Microprocessor
9.3 Self-Timed Circuit Design*
9.3.l Se1fTimed Concept
9.3.2 Completion-Signal Generation
9.3.3 Self Timed Signaling
9.4 Synchronizers and Arbiters*
9.4.1 Synchronizers--Concept and Implementation
9.4.2 Arbiters
9.5 Clock Generation and Synchronization*
9.5.1 Clock Generators
9.5.2 Synchronization at the System Level
9.6 Perspective f Synchronous versus Asynchronous Design
9.7 Summary
9.8 To Probe Further
9.9 Exercises and Design Problems
Chapter 10: Designing Memory and Array Structures
10.l Introduct1on
I0.2 Semiconductor Memories--An Introduction
10.2.1 Memory Classificat1on
l0.2.2 Memory Architectures and Building Blocks
10.3 The Memory Core
l0.3.1 Read-Only Memories
l0.3.2 Nonvolatile Read-Write Memories
l0.3.3 Read--Write Memories (RAM)
l0.4 Memory Peripheral Circuitry
10.4. l The Address Decoders
10.4.2 Sense Amplifiers
l0.4.3 Drivers/Buffers
l0.4.4 Timing and Control
l0.5 Memory Reliability and Yield
10.5.l Signal-To-Noise Ratio
10.5.2 Memory yield
l0.6 Case Studies in Memory Design
l0.6.1 The Programmable Logic Array (PLA)
l0.6.2 A 4 Mbit SRAM
l0.7 Perspective: Semiconductor Memory Trends and Evolutions
l0.8 Summary
l0.9 To Probe Further
l0.l0 Exercises and Design Problems
Chapter 11: Design Methodologies
ll.l Introduction
ll.2 Design Analysis and Simulation
ll.2.l Representing Digital Data as a Continuous Entity
ll.2.2 Representing Data as a Discrete Entity
ll.2.3 Using Higher-Level Data Models
1l.3 Design Verification
l1.3.l Electrical Verification
ll.3.2 Timing Verification
l1.3.3 Functional (or Formal) Verification
ll.4 Implementation Approaches
ll.4.l Custom Circuit Design
ll.4.2 Cell-Based Design Methodology
ll.4.3 Array--Based Implementation Approaches
ll.5 Design Synthesis
ll.5.l Circuit Synthesis
ll.5.2 Logic Synthesis
ll.5.3 Architecture Synthesis
l1.6 Validation and Testing of Manufactured Circuits
1l.6.l Test Procedure
11.6.2 Design for Testability
11.6.3 Test-Pattern Generation
ll.7 Perspective and Summary
ll.8 TO Probe Further
ll.9 Exercises and Design Problems
Problem Solutions
Index
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