Brief Contents
1 Introduction
Number Systems and Conversion
2 Boolean Algebra
3 Boolean Algebra(Continued)
4 Applications of Boolean Algebra
Minterm and Maxterm Expansions
5 Karnaugh Maps
6 Quine-McCluskey Methce
7 Multi-Level Gate Circuits
NAND and NOR Gates
8 Combinational Circuit Design and Simulation Using Gates
9 Multiplexers,Declders,and Programmable
Logic Devices
10 Introduction to VHDL
11 Latches and Flip-Flops
12 Registers and Counters
13 Analysis of Clocded Sequential Circuits
14 Derivation of State Graphs and Tables
15 Reduction of State Table
State Assignment
16 Sequential Circuit Design
17 VHDL for Sequential Logic
18 Circrits for Arithmetic Operations
19 State Machine Desingn with SM Charts
20 VHDL for Digital System Design
A Appendices
Contents
Preface
How to Use This Book for Self-Study
1 Introduxtion
Number Systems and Conversion
Objectives
Study Guide
1.1 Digital Systems and Switching Circuits
1.2 Number Systems and Conversion
1.3 Binary Arithmetic
1.4 Representation of Negative Numbers
Addition of 2's Complement Numbers
Addition fo 1's Complement Numbers
1.5 Binary Codes
Problems
2 Boolean Algebra
Objectives
Study Guide
2.1 Introduction
2.2 Basic Operations
2.3 Boolean Expressions and Truth Tables
2.4 Basic Theorems
2.5 Commutative,Associative,and Distributive Laws
2.6 Simplification Theouems
2.7 Multiplying Out and Factouing
2.8 DeMorgan's Laws
Problems
Laws and Theorems of Boolean Algebra
3 Boolean Algebra (Continued)
Objective
Study Guide
3.1 Multiplying Out and Factoring Expressions
3.2 Exclusive-OR and Factoring Expressions
3.3 The Consensus Theorem
3.4 Algebraic Simplification of Switching Wxpressions
3.5 Proving the Validity of an Equation
Programmed Exercises
Problems
4 Applications of Boolean Algebra
Minterm and Maxterm Expansions
Objectives
Study Guide
4.1 Conversion of English Sentencse to Boolean Equations
4.2 Combinational Logic Design Using a Truth Table
4.3 Mimterm and Maxterm Expansions
4.4 General Minterm and Maxterm Expansions
4.5 Incompletely Specified Functions
4.6 Examples of Truth Table Construction
4.7 Design of Binary Adders and Subtracters
Problems
5 Karnaugh Maps
Objectives
Study Guide
5.1 Minimum Forms of Switching Functions
5.2 Two-and Three-Variable Karnaugh Maps
5.3 Four-Variable Karanugh Maps
5.4 Determination of Minimum Expressions
Using Essential Prime Implicants
5.5 Five-Varable Karnaugh Maps
5.6 Other Used of Karnaugh Maps
5.7 Other Forms of Karnaugh Maps
Programmed Exercises
Problems
6 Quine-McCluskey Method
Objectives
Study Guide
6.1 Determination of Prime Implicants
6.2 The Prime Implicant Chart
6.3 Petrick's Method
6.4 Simplification of Incompletely Specified Functions
6.5 Simplification Using Map-Entered Variableds
6.6 Conclusion
Programmde Exercise
Problems
7 Multi-Level Gate CirCuits
NAND and NOR Gates
Objectives
Study Guide
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circrits Using NAND and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate Circuits
7.5 Circuit Conversion Using Alternative Gate Symbols
7.6 Delign of Two-Level,Multiple-Ortput Circuits
Determination of Essential Prime Implicants for
Multiple-Output Realization
7.7 Multiple-Output NAND and NRO Circuits
8 Combinational Circuit Design
and Simulation Using Gates
Objectives
Study Guide
8.1 Review of Combinational Circuit Design
8.2 Design of Corcuits with Limited Gate Fan-In
8.3 Gate Delays and Timing Diagrams
8.4 Hazards in Combinational Logic
8.5 Simultion and Testion of Logic Circuits
Problems
Design Problems
9 Multiplexers,Declders,and Programmable
Logic Devices
Objectives
Study Guide
9.1 Introduction
9.2 Multiplexers
9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices
Programmable Logic Arrays
Programmable Array Logic
9.7 Complex Programmable Logic Devices
9.8 Field Programmable Gate Arrays
Decomposition of Switching Fumctions
Problems
10 Introduction to VHDL
Objetives
Study Guide
10.1 VHDL Description of Combinational Circuits
10.2 VHDL Models for Multplexers
10.3 VHDL Modules
Four-Bit Full Adder
10.4 Signals and Constants
10.5 Arrays
10.6 VHDL Operators
10.7 Packages and Libraries
10.8 IEEE Stanedard Logic
10.9 Compilation and Simulation of VHDL Code
Problems
11 Latches and Flip-Flops
Objectives
Study Guide
11.1 Introduction
11.2 Set-Reset Latch
11.3 Gated D Latch
11.4 Edge-Triggerde D Flip-Flop
11.5 S-R FLIP-Flop
11.6 J-K Flip-Flop
11.7 T Flip-Flop
11.8 Flip-Flops with Additional Inputs
11.9 Summary
Prlblems
Programmde Exercise
12 Registers and Counters
Objectives
Study Guide
12.1 Registers and Register Transfers
Parallel Adder with Accumulator
12.2 Shift Registers
12.3 Design of Binary Counters
12.4 Counters for Other Sequences
Counters Design Using D Flip-Flops
12.5 Counter Design Using S-R and J-K Filp-Flops
12.6 Derivation of Flip-Flop Input Equations-Summary
Problems
13 Analysis of Clocked Sequential Circuits
Objectives
Study Guide
13.1 A Sequential Parety Checker
13.2 Analysis by Signal Tracing and Timing Charts
13.3 State Tables and Graphs
Construction and Interpretation of Timing Charts
13.4 General Models for Sequential Circuits
Programmed Exercise
Problems
14 Derivation of State Graphs and Tables
Objebtives
Study Guide
14.1 Design of a Sequence Detector
14.2 More Complex Design Problems
14.3 Guidelines rlf Comstruction of State Graphs
14.4 Serial Data Code Conversion
14.5 Alphanumeric State Graph Notation
Programmed Exercises
Probleml
15 Reduction of State Tables
State Assignment
Objectives
Study Guide
15.1 Elimination of Redundant States
15.2 Equivalent States
15.3 Determination of State Equivalence Using an Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incmpletely Specified State Tables
15.6 Derivation of Flip-Folp Input Equations
15.7 Equivalent State Assignments
15.8 Guidelines for State Assignment
15.9 Using a One-Hot State Assignment
Problems
16 Sequential Circuit Design
Objectives
Study Guide
16.1 Summary of Design Procedure for Sequential Circuits
16.2 Design Example-Code Converter
16.3 Design of Iterative Circuits
Design of a Comparator
16.4 Design of Sequential Circuits Using ROMs and PLAs
16.5 Sequential Circuit Design Using CPLDs
16.6 Sequential Circuit Design Using FPGAs
16.7 Simulation and Testing of Sequrential Circuits
16.8 Overview of Computer-Aided Design
Design Problems
Additional Problems
17 VHDL for Sequential Logic
Objectives
Study Guide
17.1 Modeling Flip-Flops Using VHDL Processes
17.2 Modeling Registers and Counters Using VHDL Processes
17.3 Modeling Combinational Logic Using VHDL Processes
17.4 Modeling a Sequential Machine
17.5 Synthesis of VHDL Code
17.6 More about Processes and Sequential Statements
Problems
Simulation Prlblems
18 Circuits for Arithmetic Operations
Objectives
Study Guide
18.1 Serial Adder with Accumulator
18.2 Design of a Parallel Multiplier
18.3 Design of a Binary Divider
Programmed Exercises
Prlblems
19 State Machine Design with SM Charts
Objectives
Study Guide
19.1 State Machine Charts
19.2 Derivation of SM Charts
19.3 Realization of SM Charts
Problems
20 VHDL for Digital System Design
Objectives
Study Guide
20.1 VHDL Code for a Serial Adder
20.2 VHDL Code for a Binary Multiplier
20.3 VHDL Code for a Binary Divider
20.4 VHDL Code for a Dice Game Simulator
20.5 Concluding Remarks
Problems
Lab Design Problems
A Appendices
A MOS and COMS Logic
B VHDL Language Summary
C Proofs of Theorems
References
Answers to Selected Study Guide
Questions and Problems
Index
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