CHAPTER 1 INTRODUCTION
1.1 The Scope of Computer Architecture and Organization
1.2 Modeling Computer Organization
1.2.1 The Layered Structure of Computer Design Process
1.2.2 The RTL Model of Computer Organization
1.2.3 The Performance Model of a Computer System
1.3 A Historical Sketch of Computer Evolution
1.4 Representative Computer Families
1.4.1 The Pentium Family
1.4.2 The SPARC Family
1.4.3 The PowerPC Family
1.5 Perspectives of the Computer Evolution
1.5.1 The Challenges of a Billion-Transistor IC
1.5.2 The New Role of the Next-Generation PC
1.5.3 Embedded Systems
1.6 Summary
CHAPTER 2 THE REPRESENTATION OF INFORMATION IN A COMPUTER
2.1 Data Types Representing Information in a Computer
2.2 Representation of Fixed-Point Unsigned Numbers
2.2.1 The General Positional Number System
2.2.2 The Representation of Fractional Numbers
2.2.3 Converstion Between Numbers of Different Representations
2.3 Representaion of Fixed-Point Signed Numbers
2.3.1 Sign-Magnitude Representation
2.3.2 Two's Complement Representation
2.3.3 Motivation for the Two's Complement System
2.3.4 One's Complement Representation
2.4 Binary Addition/Subtraction
2.4.1 Sign-Magnitude Addition/Subtraction
2.4.2 Two's Complement Addition/Subtraction
2.4.3 One's Complement Addition/Subtraction
2.5 Other Code Systems Using Bit Strings
2.5.1 Gray Codes
2.5.2 Decimal Codes
2.5.3 Character Codes
2.6 Summary
Exercieses
CHAPTER 3 LOGIC DESIGN OF COMBINATIONAL CIRCUITS
3.1 Combinational Logic Functions and Expressions
3.1.1 Using Truth Table to Define a Combinational Logic Function
3.1.2 Primitive Combinational Functions and Basic Logic Operations
3.1.3 Boolean Algebra and Logic Expression
3.1.4 Canonical Logic Expressions
3.2 Karnaugh Maps for Simplification of Logic Functions
3.3 Implementation of Combinational Logic Functions
3.3.1 AND,OR,and NOT Gates
3.3.2 NAND and NOR Gates
3.3.3 XOR and XNOR Gates
3.4 Design of Combinational Logic Corcuits
3.4.1 Design of a Full Adder
3.4.2 Ripple-Carry Adder/Subtractor with External Logic for Subtraction
3.4.3 Double Pracision Addition/Subtraction
3.4.4 Ripple-Carry Adder For Sign-Magnitude Representation
3.5 Dynamic Characteristics of Combinational Logic Circuits
3.5.1 Propagation Delay of Combinational Logic Circuits
3.5.2 Waveform Diagram of Combinational Logic Circuits
3.5.3 Hazards in Combinational Logic Circuits
3.6 Combinational MSI Modules
3.6.1 Multiplexer
3.6.2 Decoder/Demultiplexer
3.6.3 Encoder
3.7 Programable Logic Devices
3.7.1 Programmable Logic Array(PLA)
3.7.2 Read-Only Memory(ROM)
3.7.3 Programmable Array Logic(PAL)
3.7.4 Complex Programmable Logic Devices(CPLDs)
3.7.5 Field-Programmable Gate Arrays(FPGAs)
3.8 Summary
Exercises
CHAPTER 4 LOGIC DESIGN OF SEQUENTIAL CIRCUITS
4.1 General Model of Sequential Circuits
4.2 Flip-Flops
4.2.1 Analysis of A Simple SR Latch
4.2.2 SR Flip-Flop
4.2.3 JK Flip-Flop
4.2.4 T Filp-Flop
4.2.5 D Filp-Flop
4.2.6 Practical Flip-Flop Circuits
4.3 Analysis of Sequential Logic Circuits
4.3.1 From Circuit to State-Transition Diagram
4.3.2 From State-Transition Diagram to Finite State Machine
4.4 Synthesis of Sequential Logic Circuits
4.5 Sequential MSI Modules
4.5.1 Register
4.5.2 Shift Register
4.5.3 Counter
4.6 Design of a Finite-State Machine
4.7 Summary
Exercises
CHAPTER 5 THE ARITHMETIC LOGIC UNIT
5.1 The von Neumann Computer Model
5.2 Parallel Fast Adders
5.2.1 The Nature of Carry Propagation
5.2.2 The Ripple-Carry Parallel Adder(Revisited)
5.2.3 The Four-bit Carry Look-ahead Adder
5.2.4 The Block Carry Look-ahead Circuit
5.3 Analysis of the Design of a Commercial ALU Chip
5.3.1 Organization of an ALU Based on an Adder
5.3.2 Design of the Input Circuit for Logic Operations
5.3.3 Analysis of the AUL for Arithmetic Operations
5.4 Methodes for Designing Arithmetic-Logic Units
5.4.1 Designing the AUL Using Extrnal Gates for Logic Operations
5.4.2 Designing the ALU Based on Standard ALU Chips
5.4.3 Redesigning the Input Circuit for the ALU
5.4.4 Designing an ALU Using the Internal Circuit of an Adder
5.4.5 Redesigning the Output Circuit of the Adder
5.4.6 Comparison of Different Methods of Designing an ALU
5.5 Incorporating a Shifter in an ALU
5.5.1 Design of a Built-in Shifter in an ALU
5.5.2 Design of the Shifter as an Independent Unit
5.5.3 Design of a Barrel Shifter
5.6 Summary
Exercises
CHAPTER 6 COMPLEX ARITHMETIC OPERATIONS
6.1 Single-Precision Multiplication
6.1.1 The Basic Algorithm for Two's Complement Multiplication
6.1.2 Fast Multiplication
6.2 Double-Precision Multiplication
6.2.1 Special Requirement for the Algorithm
6.2.2 The Algorithm for Double-Precision Multiplication of Positive Numbers
6.2.3 The Algorithm for Double-Precision Multiplcation of Two's Complement Numbers
6.3 Single-Precision Division
6.4 Double-Precision Division
6.4.1 Special Requirements of the Algorithm
6.4.2 The Algorithm for Double-Precision Division of Fractional Numbers
6.4.3 The Algorithm for Double-Precision Division of Integer Numbers
6.5 Floating-Point Operations
6.5.1 The Representation of Floating-Point Numbers
6.5.2 The Algorithms for Floating-Point Operations
6.5.3 A Complete Algorithm for Floating-Point Addition/Subtraction
6.5.4 Implementation of Floating-Point Addition/Subtraction by Sequential Logic
6.6 Summary
Exercises
CHAPTER 7 INSTRUCTION SET ARCHITECTURE
7.1 The Instruction Format
7.2 The Addressing Modes
7.2.1 Specifying the Operand in the Instruction Code
7.2.2 Specifying the Operand in a Register
7.2.3 Specifying the Operand in Memory
7.2.4 Specifying a Location Inside the Assembly-Language Program Code
7.2.5 A Case Study of Addressing Modes
7.3 Instruction Set Design
7.3.1 Data Movement Instructions
7.3.2 Arithmetic-Logic Instructions
7.3.3 Control Instructions
7.4 Reduced Instruction Set Computers(RISC)
7.5 Summary
Exercises
CHAPTER 8 THE CENTRAL PROCESSING UNIT
8.1 The Functions and Functional Parts of a CPU
8.2 The Basic Organization of The CPU
8.2.1 CPU Organization Based on General-Purpose Registers
8.2.2 CPU Organization Based on an Accumulator
8.2.3 CPU Organization Based on a Processor Stack
8.3 The Structure of a CPU Based on an Accumulator
8.3.1 Design of an Accumulator-Based CPU Built on a Single Bus
8.3.2 Design of a Tow-Bus or Three-Bus Acxcumulator-Based CPU
8.3.3 Design of an Accumulator-Based CPU Built on an ALU
8.4 The Structure of a CPU Based on General-Purpose Registers
8.4.1 The Structure of a General-Prupose Register Set
8.4.2 Design of a CPU Based on General-Prupose Registers
8.5 CPU Bit-Slice Device-A Case Study
8.6 Summary
Exercises
CHAPTER 9 THE XONTROL UNIT
9.1 Functions and General Organization of a Control Unit
9.2 Preliminaries of Designing Control Circuits
9.2.1 Control Voltage Signals vs.Control Pulse Signals
9.2.2 Design of a Signal Generator Based on a Counter
9.2.3 Synchronous Control vs.Asynchronous Control
9.2.4 Asychronous Circuits of Signal Generators
9.3 Design of the Sequential Control of Arithmeic Operations
9.3.1 Design of a Bit-Serial Adder
9.3.2 Design of a Sequential Two's Complement Multiplier
9.4 Design of Hardwired Control of a Simple Computer
9.4.1 Specification of a Simple RISC Processor
9.4.2 The Basic Instruction Cyc;e
9.4.3 Design of the Operation Chart for the Instruction Set
9.4.4 Design and Implementation of the Control Signals
9.4.5 Design and Implementation of the Datapath and Timing Signals
9.5 Design of the Microprogrammed Control of a Simple Computer
9.5.1 General Considerations for Microprogrammed Control
9.5.2 Design of the Datapath for Microprogrammed Control
9.5.3 Design of the Micrioinstruction Format for Microprogrammed Control
9.5.4 Design of the Folwchart for Microprogrammed Control
9.5.5 Obtaining the Microrogram List
9.6 Summary
Exercises
CHAPTER 10 PRIMARY MEMORY
10.1 The Memory Hierarchy
10.1.1 The Hierarchical Organization of a Memory System
10.1.2 Functionality and Performance of a Memory Hierarchy
10.2 The Organization of Main Memory
10.2.1 Functions and Characteristics of RAM Chips
10.2.2 Internal Organization of a RAM Chip
10.2.3 Basic Operations for Accessing RAM
10.2.4 Interconnection of RAM Chips for Larger Capacity
10.3 RAM Techniques for Enhanced Performance
10.3.1 Asynchronous DRAM
10.3.2 FPM and EDO
10.3.3 Synchronus DRAM(SDRAM)
10.3.4 Rambus DRAM(RDRAM)
10.3.5 Flash Memory vs.EEPROM
10.3.6 Split Bus
10.4 Cache Memory
10.4.1 Locality of Memory References
10.4.2 Mapping Functions
10.4.3 Write Policies
10.4.4 Replacement Algorithms
10.4.5 Cache Organization and Performance
10.5 Overall Primary Memory Organization
10.5.1 Serial-Memory Narrow-Bus Organization
10.5.2 Parallel-Memory Wide-Bus Organization
10.5.3 Parallel-Memory Narrow-Bus Organization
10.5.4 Interleaved-Memory Narrow-Bus Organization
10.6 Summary
Exercises
CHAPTER 11 INPUT/OUTPUT
11.1 Functions and Characteristics of I/O Subsystem
11.2 Secondary Storage
11.2.1 Magetic Disk
11.2.2 Redundant Array of Independent Disds(RAID)
11.2.3 Optical Disks
11.2.4 Magnetic Tapes
11.3 Input/Output Accessing
11.3.1 Addressing I/O Registers
11.3.2 Programmed I/O
11.3.3 Interrupt-Driven I/O
11.3.4 Direct Memory Access
11.4 Exception and Exception Handling
11.4.1 Interrup Request and Interrupt Acknowledge
11.4.2 Interrup Identification
11.4.3 Interrup Servicing and Interrupt Returning
11.5 The I/O Interfaces
11.5.1 I/O Bus Protocol
11.5.2 Parallel I/O Ports
11.6 Serial I/O Data Communication
11.6.1 Timing Synchroniation of Serial Transmission
11.6.2 Error Detection and Correction Codes
11.6.3 Serial Interfaces and I/O Ports
11.7 Bus Standards
11.7.1 PCI(Peripheral Component Interconnect)Bus
11.7.2 SCSI(Small Computer System Interface)Parallel Interface
11.7.3 The USB Serial Bus
11.7.4 The FireWire Serial Bus
11.7.5 Switched-Fabric Architecture and InfiniBand
11.8 Summary
Exercises
CHAPTER 12 PIPELINING
12.1 The Basic Concept of Pipelining
12.1.1 Parallelism in Time vs.Parallelism in Space
12.1.2 Temporal Parallelism in Pipelining
12.1.3 Performance of the Pipeline
12.2 General Organization of a Pipeline
12.2.1 Synchronous Pipeline
12.2.2 Asynchronous Pipeline
12.3 Design of a Pipeline by Way of Functional Decomposition
12.3.1 Special Properties of Instruction Pipelins
12.3.2 The Mappping of the Dataflow Pattern to the Pipeline
12.3.3 Design of the Basic Datapath of the Pipeline
12.4 The Design of the Pipeline form Hazard Analysis
12.4.1 Structural Hazards
12.4.2 Data Hazards-A General Discussion
12.4.3 Data Hazard Analysis
12.4.4 Control Hazards
12.4.5 The Complete Datapath of the Pipeline
12.5 Superscalar Processor
12.5.1 Special Featrues of a Superscalar Processor
12.5.2 Conceptual Structure of a Superscalar Processor
12.5.3 Instruction-Issue and Instruction-Execute Policies
12.6 Summary
Exercises
REFERENCES
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