CHAPTER Introduction
1．1 A Brief Historv
1．2 Book Summarv
1．3 MOS Transistors
1．4 CMOS Logic
1．4．1 The Inverter
1．4．2 The NAND Gate
1．4．3 Combinational Logic
1．4．4 The NOR Gate
1．4．5 Compound Gates
1．4．6 Pass Transistors and Transmission Gates
1．4．7 Tristates
1．4．8 Mmdplexers
1．4．9 Latches and Flip—Flops
1．S CMOS Fabrication and Lavout
1．5．1 Inverter Cross—section
1．5．2 Fabrication Process
1．5．3 ．Layout DesigTl Rules
1．5．4 Gate Lavout
1．5．5 Stick Design Rules
1．6 Design Panitioning
1．7Example:A Simple MIPS Microprocessor
1．7．1 MIPS Architecture
1．7．2 MulticVCle MIPS Microarchitecture
1．8 Logic Desiin
1．8．1 Top-1evel Interface
1．8．2 Block Diaizram
1．8．3 Hierarchv
1．8．4 Hardware Descri—on Languages
1．9Circuit Description Languages
1．10 Phvsical Design
1．10．1 Floorplanning
1．10．2 Standard Cells
1．10．3 Snap—together Ceus
1．10．4 Slice P1ans
1．10．5 Area Estimation
1．11 Design Verification
1．12 Fabl-ication，Packaging，and Testing
Summarv
Exercises
CHAPTER 2 MOS Transistor Theory
2．1 Introduction
2．2 Ideal I-V Characteristics
2．3 C—V Chara~teristics
2．3．1 Simpk MOS Capacitance Models
2．3．2 Detailed Mos Gate capacitance Model
2．3．3 Detailed Mos Diffusion Capacitance Model
2．4 Nonideal -V Effects
2．4．1 Velocity Saturation and Mobmty Degradation
2．4．2 Channel Length Modulation
2．4．3 Bodv Efiect
2．4．4 Subthreshold Conduction
2．4．5 Tunction Leakage
2．4．6 Tunnehng
2．4．7 Temperature Dedendence
2．4．8 Geometry Dedendence
2．4．9 Summalw
2．5 DC Transfer Characteristics
2．5．1 Complementalw CMOS Inverter DC Characteristics
2．5．2 Beta Rati0 Efiects
2．5．3 Noise Margin
2．5．4 Ratioed Inverter Transfer Function
2．5．5 Pass Trartsistor DC Characteristics
2．5．6 Tristate Inverter
2．6 Switch-1evel RC Delav Models
2．7Piftalls and Fallacies
Summaw
Exercises
CMOS Processing Technology
3．1 Introduction
3．2 CMOS Technologies
3．2．1 Backuxound
3．2．2 Wafer Formation
3．2．3 Photolithography
3．2．4 WeU and Channel Formation
3．2．5 Smcon Dioxide(Si02)
3．2．6 Isolation
3．2．7 Gate Oxide
3．2．8 Gate alld Soufce／Drain Formation
3．2．9 Contacts and Metauization
3．2．10 Passivation
3．2．11 Metrolon
3．3 Layout Design Rules
3．3．1 Design Rule Background
3．3．2 Scribe Line and Other Structures
3．3．3 MOSIS Scalable CMOS Design Rules
3．3．4 Micron Design Rules
3．4 CMOS Process Enhancements
3．4．1 Transistors
3．4．2 Interconnect
3．4．3 Cirucit Elements
3．4．4 Beyond Conventional CMOS
3．5 Technology-related CAD Issues
3．5．1 Design Rule Checl(ing(DRC)
3．5．2 Circuit Extraction
3．6 Manufacturing Issues
3．6．1 Antenna Rules
3．6．2 Layer Dcnsit Rules
3．6．3 Resolution Enhancement Rules
3．7Pitfalls and Fallacies
3．8 Historical Perspective
Summarv
Exercises
CHAPTER 4 Circuit Characterization and
Performance Estimation
4．1 Introduction
4．2 Delav Estimation
4：2．1 RC Delav Models
4．2．2 Linear Delav Model
4．2．3 Logical Efrort
4．2．4 Parasitic Delay
4．2．5 Limitations to the Linear Delay Model
4．3 Logical Effort and Transistor SIzing
4．3．1 Delav in a logic Gate
4．3．2 Delay in Multistage L0gic Networks
4．3．3 Choosing the Best Number 0f Stages
4．3．4 Exampk
4．3．5 Summary and Observations
4．3．6 Limitadons of Logical Efrort
4．3．7 Extracting Logical Efrort from Datasheets
4．4 Power Dissipation
4．4．1 Static Dissipation
4．4．2 Dvnamic Dissipation
4．4．3 Low-power Design 191
4．5 Interconnect
4．5．1 Resistance
4．5．2 Capadtance
4．5．3 Delay
4．5．4 Crosstalk
4．5．5 Inductance
4．5．6 Tempe：rature Dependence 216
4．5．7 An Aside on Efiectivc Resistance and Elmore Delay
4．6 Wire Engineering
4．6．1 Width and Spadng
4．6．2 Layer Sekction
4．6．3 Shielding
4．6．4 Repeaters 221
4．6．5 Implications for Logical Efrort
4．6．6 crosstalk Control
4．6．7 LOW-swing signallng
4．7 Design Margin
4．7．1 Supplv Vohage
4．7．2 Temperature
4．7．3 Process Variation
4．7．4 Design Comers
4．7．5 Matching
4．7．6 Delay Tracking
4．8 Reliabilitv
4．8．1 Reliabmty Terminolo
4．8．2 Electromigration
4．8．3 SeIf-heating
4．8．4 Hot Carriers
4．8．5 Latchup
4．8．6 Overv01tage Failure
4．8．7 Soft Etrots
4．9 Scaling
4．9．1 Transistor Scaling
4．9．2 Interconnect Scaling
4．9．3 Intemational Technology Roadmap for Semiconductors
4．9．4 Impacts on Design
4．10Pitfalls and Fallacies
4．11 Historical Perspective
Summary
Exercises
CHAPTER 5 Circuit Simulation
S．1 IntrOduction
5．2 A SPICE Tutorial
5．2．1 Sourccs and Passiv Components
5．2．2 Trartsistor DC Analvsis
5．2．3 Inverter Transient Analvsis
5．2．4 Subcircuits and Measurement
5．2．5 OptiInization
5．2．6 Other HSPICE Commands
5．3 Derice M0dels
5．3．1 Level 1 Models
5．3．2 Level2 and 3 Models
5．3．3 BSIM M0dels 288
5．3．4 Diffusion Capacitance Models
5．3．5 Design Comers
5．4 Device Characterization
5．4．1 I-V Characteristics
5．4．2 Tlareshold Voltage
5．4．3 Gate Capacitance
5．4．4 Parasitic Capacitance
5．4．5 Efiective Resistance
5．4．6 C0mparison of Processes
5．4．7 Process and Environmental Sensitivity
5．5 Circuit Charaterization
5．5．1 Path Simmations
5．5．2 DC Trartsfer Characteristics
5．5．3 Logical Effort
5．5．4 Power and Energy
5．5．5 Simulatinff Mismatches
5．5．6 Monte Carlo Simulation
5．6 Interconnect Simulation
5．7Piftalls and Fallacies
Summar
Exercises
CHAPTER 6 Combinational Circuit Design
6．1 Introduction
6．2 Circuit Famnies
6．2．1 Static CMOS
6．2．2 Ratioed Circuits
6．2．3 Cascode Voltage Switch Logic
6．2．4 Dynamic Circuits
6．2．5 Pass—transistor Circuits
6．3 Circuit Pitfaus
6．3．1 Threshold Drops
6．3．2 Ratio Failures
6．3．3 Leakage
6．3．4 Charise Sharing
6．3．5 Power Supply Noise
6．3．6 H0t Spots
6．3．7 Minority Cartier Injectioon
6．3．8 Back_ffate Coupling
6．3．9 Diflusion Input Noise Sensitivity
6．3．1Oprocess Scnsitivity
6．3．1Example:Domino Noise budgets1
6．4 More circuit Families
6．4．1 Difiercntial Circuits
6．4．2 Sensc—amplifier Circuits
6．4．3 BiCMOS Circuits
6．4．4 Other Circuit Fammes
6．5 LOW—power Lo百c Design
6．6 Comparison Of CirCUit Families
6．7 Silicon-on-Insulator Circuit Design
6．7．1 F10ating Body Vohage
6．7．2 SoI Advantages
6．7．3 SoI Disadvantages
6．7．4 Implicatioms for Circuit Stvles
6．7．5 Summarv
6．8Piftalls and Fallacies
6．9 Historical Perspective
Summarv
ExerciSes
Sequential Circuit Design
7．1 Introduction
7．2 Sequencing Static Circuits
7．2．1 Sequencing Methods
7．2．2 Max—Delay Constrajnts
7．2．3 Min—delay Constraints
7．2．4 Time Borrowing
7．2．5 Clock Skew 399
7．3 Circuit Design of Latches and Flip-flops
7．3．1 Conventional CMOS Latches
7．3．2 Conventional CMOS Flipp—llops
7．3．3 Pulsed Latehes
7．3．4 Resettable Latches and Flip—flops
7．3．5 Enabled Latches and Flip—floos
7．3．6 Incorporating Logic into Latches
7．3．7 K1ass Semidvnamic Flip—floo(SDFF)
7．3．8 Difierential Flip—flops 412
7．3．9 True Si．gle—phase—clock(TSPC)Latehes and FliP—flops
7．4 Static Sequencing Element Meethodology
7．4．1 Choice of E1ements
7．4．2 Low-power Sequential Design
7．4．3 Two—phase Timing Types
7．4．4 Characterizing Sequencing Element Delays
7．5 sequencing Dynamic Circuits
7．5．1 Tradi60nal Domino Circuits
7．5．2 Skew-tolerant Domino Circuits
7．5．3 Unfooted Domin0 Gate Timing
7．5．4 Nonmonotonic Techniques
7．5．5 Static—to—domino Interface
7．5．6 Delayed Keepers
7．6 synchronizers
7．6．1 Metastabmt
7．6．2 A Simple Synchromzer
7．6．3 Commumcatink Between Asynchronous Clock Domains
7．6．4 Common Synchronizer Mistakes
7．6．5 Arbiters
7．6．6 Degrees of Synchrony
7．7 Wave Pipelining
7．8Piftalls and Fallacies
7．9 Case Study：Pentium 4 and Itanium 2
Sequencing Methodologies
7．9．1 Pentium 4 Sequencing
7．9．2 Itanium 2 Sequencing
Summarv
Exercises
Design Methodology and Tools
8．1 Introduction
8．2 Structured Design Strategies
8．2．1 A Software Radio--A System Example
8．2．2 Hierarchv
8．2．3 Remlarity
8．2．4 Modularity
8．2．5 Locality
8．2．6 Summary
8．3 Design Methods
8．3．1 Microprocessor／DSP
8．3．2 Proammable Logic
8．3．3 Gate Array and Sea 0f Gates Design 507
8．3．4 Cell-based Design
8．3．5 Full Custom Design
8．3．6 Platform—based Design一System on a Chip
8．3．7 Summaly
8．4 DeSign FlOWS
8．4．1 Behavioral Syndlesis Design Flow(ASIC Design Flow) 522
8．4．2 Automated Layout Generation
8．4．3 Mixed—signal 0r Custom—desi Folw
8．4．4 Prozrammed Behavioral Synthesis 535
8．5 DeSign Economics
8．5．1 Non—recurring E11g111eering Costs(NREs)
8．5．2 Recurrin Costs
8．5．3 Fixed Costs
8．5．4 Schedule
8．5．5 Personvower
8．5．6 Proiect Manaement
8．5．7 Design Reuse
8．6 Data Sheets and Documentation
8．6．1 The Summary
8．6．2 Pinout
8．6．3 Description 0f operation
8．6．4 DC Speciticatlolls
8．6．5 AC Specifications
8．6．6 Package Diagram
8．6．7 Principks 0f Operation Manual
8．6．8 User Manual
8．7 Closing the Gap betwceil ASIC and Custom
8．7．1 MicroRrchitecture
8．7．2 Sequendng Overhead
8．7．3 Circuit Families
8．7．4 Logic Design
8．7．5 CeU and Wire Design
8．7．6 Lavout
8．7．7 Process Variation
8．7．8 Summarv
8．8 CMOS Physical Design Styles
8．8．1 Static CMOS Gate Layout
8．8．2 Gelleral CMOS Layout Guidehlles
8．8．3 Layout optimization for Performance
8．9 Interchange Formrts
8．9．1 GDS2 Stream
8．9．2 Caltech Interme(1iate Format(CIF)
8．9．3 Library Exchange Format(LEF)
8．9．4 Design Exchange Format(DED
8．9．5 Standard Delay Format(SDF)
8．9．6 DSPF and SPEF
8．9．7 Advanced LibrarF Format(ALF)
8．9．8 WAVES Waveforrn and Vector Exchanffe Specmcation
8．9．9 Physical Design Exchange Format(PDEF)
8．9．1 0 OoenAccess
8．10 Historical Perspective
8．11Piftalls and fallacies
Exercises
CHAPTER 9 Testing and Verification
9．1 Introduction
9．1．1 Logic Verification
9．1．2 Basic Digital Debugging Hints
9．1．3 Manufacturing Tests
9．2 Testers Test Fixtures and Test Programs
9．2．1 Testers and Tost Fixtures 575
9．2．2 Test Prolrams
9．2．3 Handkrs
9．3 Logic Veriflcation Plinciples
9．3．1 Test Benches and Hamesses
9．3．2 Regression Testing
9．3．3 Version Control
9．3．4 Bug Tracliing
9．4 Silicon Debug P1inciples
9．5 Manufacturing Test Principles
9．5．1 Fault M0dels
9．5．2 Observabmnr
9．5．3 Controuability
9．5．4 Fault Coverae
9．5．5 Automatic Test Pattem Generation(ATPG)
9．5．6 DelayFaultTestinff
9．6 Design for Testability
9．6．1 Ad boc testinff
9．6．2 Scan Design
9．6．3 Builtyin Self-Test(BIST)
9．6．4 IDDQ．Testing 608
9．6．5 Design for Manufacturability
9．7 BoundaIw Scan
9．7．1 TheTest Access Port(TAP)
9．7．2 The Test L0gic Architecture and Test Access Port
9．7．3 The TAP Controlier
9．7．4 The Instruction Register
9．7．5 Test Data Registers
9．7．6 Summary
9．8 System—on—chip(SOC)Testing
9．9 Mixed—signal Testing
9．10 Reliability Testing
9．11 Testing in a University Environment
9．12Piftalls and fallacies
Summary
ExerCises
CHAPER 10 Datapath Subsystems
10．1 Inttoduction
10．2 AdditiordSubtraction
10．2．1 Sin-BIe．bit Addition
10．2．2 Cany—Propagate Adclin
l0．2．3 Adder Variallts 677
10．3 One／Zeleo Detectors
10．4 COmpaTators
10．4．1 Magnimde Compator
10．4．2 Equdity Comp~ator
10．4．3K=A+B Comparator
10．5 Counters
10．5．1 Binary Counters
10．5．2 Linear—feedback Shilt Registers 684
10．6 Boolean Logical OpeTations
10．7 Coding
10．7．1 Parity
l0．7．2 EITOr—correcting Codes
10．7．3 Grav Codes
10．7．4 XOR／XNOR Circuit Forms
10．8 Shifters
10．9 Multiplication
10．9．1 Unsigned Array Multiphcation
10．9．2 2，s Complement Artay Mulfiplication
10．9．3 Booth Enco1ing
10．9．4 Wdlace Tree Multiplication
10．9．5 Hybrid Multiplication
10．9．6 Fused Multiply-Add
10．9．7 serial Multiphcation
10．10 Parallel一prefix Computations
10．11Pitfalls and Fallacies
10．12 Historical Perspective
Summflry
Exercises
CHAPTER 11 Array Subsystems
11．1 Introcuction
11．2 SRAM
11．2．1 Memory CeU Read／Wfite Operadon
11．2．2 Decoders
11．2．3 BithRe ConditioninK aJld Column Circukry
11．2．4 Multi．ported sRAM and Register Files
11．2．5 Large SRAMs
11．2．6 Logical Efrort of RAMs and Register Files
11．2．7 case Study：Itanium 2 Cache
11．3 DRAM
11．3．1 Subarray Architectures
11．3．2 column circukry
11．3．3 ApPhcadons to CMOS Systerns—on—chip
11．4 Read—only Memory
11．4．1 Programmable ROMs
11．4．2 NAND ROMs
11．5 Serial Access Memories
11．5．1 Shm Registers
11．5．2 Queues(FIFO，LIFo)
11．6 Content．addressable Memory
11．7 Programmable Logic Atrays
11．8 Arra Yield,Reliability,and Self test
11．9 Historical Perspective
Summary
Exercj ses
CHAPTER 12 Special-purpose Subsystems
12．1 Introduction
12．2 Packaging
12．2．1 Package options
12．2．2 Chip—to—package Connections
12．2．3 Packare Parasi6cs
12．2．4 Heat Dissipafion
12．3 Power Distl-ibution
12．3．1 On—chip Power Distribudon Network
12．3．2 IR Drods
12．3．3 L di／dt N0ise
12．3．4 On—chip Bypass Capacitance
12．3．5 Power Network Modeling
12．3．6 Signal Return Paths
12．3．7 Power supply Filtering
12．3．8 Substrate Noise
12．4 I／O
12．4．1 Basic I／O Pad Circuits
12．4．2Example:MosIs I／0 Pads
12．4．3 Level Converters
12．5 Clock
12．5．1 Definitions
12．5．2 Clock System Arcmtecture
12．5．3 G10bal C10Ck Generation
12．5．4 G10bal Clock Distributioll
12．5．5 Local CloCk Gaters
12．5．6 Clock Skew Budgets
12，5．7 Adaptive Deskewing
12．5．8 Clocking Alternatives
12．6 Analog Circuits
12．6．1 MOS Small—signal Model
12．6．2 Common Source Amplifter
12．6．3 The CMOS Inverter as an Amplifier
12．6．4 Current Mirrors
12．6．5 Difietential Pairs
12．6．6 Simple CMOS operadonal Amplifier
12．6．7 Digital—t0一analog and Analog—to-digital converter Basics
12．6．8 Digital一to—analol Converters
12．6．9 Analog—t0一digital Converters
12．6．10 Ra(1io Frequency(RF)Circuits
12．6．11 Analog Summary
12．7 Piftalls and fallacies
12．8 Historica Perspective
Summarv
Exercises
APPENDIX A Verilog
A．1 Introduction
A．2 Behavioral Modeling With Continuous Assignments
A．2．1 Bimdse Operators
A．2．2 Comments and White Srace
A．2．3 Reduction Ooerators
A．2．4 Other Orators
A．3 Basic Constructs
A．3．1 Intemal Signals
A．3．2 Precedence
A．3．3 Constants
A．3．4 Hierarchv
A．3．5 Tristates
A．3．6 Bit Swizzling
A．3．7 Delays
A．4 Behavioral Modeling with Alwalvs Blocks
A．4．1 Registers
A．4．2 Latches
A．4．3 Counters
A．4．4 Combinadonal Logic
A．4．5 Memories 866
A．4．6 Bloclcing and Nonblocking Assignment
A．5 Finite State Machines
A．6 Parameterized Modules
A．7 Structural Primitives
A．8 Test Benches
A．9 Pitfalls
A．9．1 Verilog Style Guidelincs
A．9．2 Incorrect Stimulus List
A．9．3 Missing begin／end Block
A．9．4 Undefined Outputs
A．9．5 Incompkte Specification 0f Cases
A．9．6 Shorted Outputs 884
A．9．7 Incorrect Use 0f Nonblocking Assignments
A．10Example:MIPS Processor
APPENDIX B VHDL
B．1 Introduction
B．2 Behavioral Modeling with Concurrent Signal Assignments
B．2．1 Bitwise operators
B．2．2 Comments and Wmte Space
B．2．3 other operators 897
B．2．4 Conditional Signal Assignment Statements
B．2．5 Selected Signal Assignment Statements
B．3 Basic Constructs
B．3．1 Blocks，Entities，and Architectures
B．3．2 Internal Signals
B．3．3 Precedence
B．3．4 Hierarchy
B．3．5 Bit Swizzling
B．3．6 Types
B．3．7 Libralw and Use Clauses
B．3．8 Tristates
B．3．9 Delays
B．4 Behavioral Modeling With Process Statements
B．4．1 Flip—flops
B．4．2 Latches
B．4．3 Counters
B．4．4 Combinational Logic
B．4．5 Memories
B．5 Finite State Machines
B．6 Parameterized Blocks
B．7Example:MIPS Processor
References
Index
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