Preface
Glossary
Abbreviations
1 Digital to Analog conversion concepts
1.1 Functional aspects
1.1.1 Definition of the D/A function
1.1.2 Functional specifications
1.2 Algorithmic aspects
1.3 Signal processing aspects
1.3.1 Waveforms and Line coding
1.3.2 Signal Modulation concepts
1.4 Circuit aspects
1.4.1 Architecture terminology
1.4.2 Resistive voltage division architectures
1.4.3 Capacitive voltage and charge division architectures
1.4.4 Current division based architectures
1.5 Conclusions
2 Framework for Analysis and Synthesis of DACs
2.1 Overview
2.2 Framework description
2.2.1 Analysis
2.2.2 Synthesis
3 Current Steering DACs
3.1 Basic circuit
3.1.1 Partitioning and segmentation
3.1.2 Current switching network and current sources
3.1.3 Clock-data synchronization circuit
3.1.4 Auxiliary circuits
3.2 Implementations and technology impact
4 Dynamic limitations of Current Steering DACs
4.1 State of the art in dynamic linearity
4.2 Dynamic limitations of current steering DACs
4.2.1 Matching and relative amplitude precision
4.2.2 Matching and relative timing precision
4.3 Conclusions
5 Current Steering DAC circuit error analysis
5.1 Amplitude domain errors
5.1.1 Relative amplitude inaccuracies
5.1.2 Output resistance modulation
5.2 Time domain errors
5.2.1 Nonlinear settling and output impedance modulation
5.2.2 Asymmetrical switching
5.2.3 Modulation of switching behavior
5.2.4 Charge feedthrough and injection
5.2.5 Relative timing inaccuracies
5.2.6 Power supply bounce and substrate noise
5.2.7 Clock (timing) jitter
5.3 Conclusions
6 High-level modeling of Current Steering OACs
6.1 System modeling
6.1.1 System layers
6.1.2 System excitations and responses
6.1.3 System parameters
6.1.4 Subsystem interaction
6.1.5 System modulation
6.2 Error properties and classification
6.2.1 Error properties
6.2.2 Error classification
6.3 Functional error generation mechanisms
6.3.1 Definitions
6.3.2 Algorithmic modeling
6.3.3 Functional modeling
6.3.4 Examples
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7 Functional modeling of timing errors
8 Functional analysis of local timing errors
9 Circuit analysis of local timing errors
10 Synthesis concepts for CS DACs
11 Design of a 12 bit 500 Msample/s DAC
References
A Output spectrum for timing errors
B Literature data
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