1 Device Physics.
1.1 Semiconductors
1.2 PN Junctions
1.3 Bipolar Junction Transistors
1.4 MOS Transistors
1.5 JFET Transistors
1.6 Summary
1.7 Exercises
2 Semiconductor Fabrication
2.1 Silicon Manufacture
2.2 Photolithography
2.3 Oxide Growth and Removal
2.4 Diffusion and Ion Implantation
2.5 Silicon Deposition and Etching
2.6 Metallization
2.7 Assembly
2.8 Summary
2.9 Exercises
3 Representative Processes
3.1 Standard Bipolar
3.2 Polysilicon-Gate CMOS
3.3 Analog BiCMOS
3.4 Summary
3.5 Exercises
4 Failure Me hanisms
4.1 Electrical Overstress
4.2 Contamination
4.3 Surface Effects
4.4 Parasitics
4.5 Summary
4.6 Exercises
5 Resistors
5.1 Resistivity and Sheet Resistance
5.2 Resistor Layout
5.3 Resistor Variability
5.4 Resistor Parasitics
5.5 Comparison of Available Resistors
5.6 Adjusting Resistor Values
5.7 Summary
5.8 Exercises
6 Capacitors and Inductors
6.1 Capacitance
6.2 Inductance
6.3 Summary
6.4 Exercises
7 Matching of Resistorscand Capacitors
7.1 Measuring Mismatch
7.2 Causes of Mismatch
7.3 Rules for Device Matching
7.4 Summary
7.5 Exercises
8 Bipolar Transistors..
8.1 Topicscin Bipolar Transistor Operation
8.2 Standard Bipolar Small-Signal Transistors
8.3 CMOS and BiCMOS Small-Signal Bipolar Transistors
8.4 Summary
8.5 Exercises
9 Applications of Bipolar Transistors
9.1 Power Bipolar Transistors
9.2 Matching Bipolar Transistors
9.3 Rulescfor Bipolar Transistor Matching
9.4 Summary
9.5 Exercises
10 Diodes
10.1 Diodescin Standard Bipolar
10.2 Diodescin CMOS and BiCMOS Processes
10.3 Matching Diodes
10.4 Summary
10.5 Exercises
11 Field-Effect Transistors
11.1 Topicscin MOS Transistor Operation
11.2 Constru ting CMOS Transistors
11.3 Floating-Gate Transistors
11.4 The JFET Transistor
11.5 Summary
11.6 Exercises
12 Applications of MOS Transistors
12.1 Extended-Voltage Transistors
12.2 Power MOS Transistors
12.3 MOS Transistor Matching
12.4 Rules for MOS Transistor Matching
12.5 Summary
12.6 Exercises
13 Special Topics
13.1 Merged Devices
13.2 Guard Rings
13.3 Single-level Interconnection
13.4 Constructing the Padring
13.5 ESD Struc tures
13.6 Exercises
14 Assembling the Die
14.1 Die Planning
14.2 Floorplanning
14.3 Top-Level Interconnection
14.4 Conclusion
14.5 Exercises
Appendices
A. Table of A ronyms Used in the Text
B. The Miller Indices of a Cubi Crystal
C. Sample Layout Rules
D. Mathematical Derivations
E. Sources for Layout Editor Software
Index
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