Table of Contents
Additional Resources
Preface
1 Processor Design
1.1 The Evolution of Microprocessors
1.2 Instruction Set Processor Design
1.2.1 Digital Systems Design
1.2.2 Architecture, Implementation, and Realization
1.2.3 Instruction Set Architecture
1.2.4 Dynamic-Static Interface
1.3 Principles of Processor Performance
1.3.1 Processor Performance Equation
1.3.2 Processor Performance Optimizations
1.3.3 Performance Evaluation Method
1.4 Instruction-LevelParallel Processing
1.4.1 From Scalar to Superscalar
1.4.2 Limits of Instruction-Level Parallelism
1.4.3 Machines for Instruction-Level Parallelism
1.5 Summary
2 Pipelined Processors
2.1 Pipelining Fundamentals
2.1.1 Pipelined Design
2.1.2 Arithmetic Pipeline Example
2.1.3 Pipelining Idealism
2.1.4 Instruction Pipelining
2.2 Pipelined Processor Design
2.2.1 Balancing pipeline Stages
2.2.2 Unifying Instruction Types
2.2.3 Minimizing Pipeline Stalls
2.2.4 Commercial Pipelined Processors
2.3 Deeply Pipelined Processors
2.4 Summary
3 Memory and l/O Systems
3.1 Introduction
3.2 Computer System Overview
3.3 Key Concepts: Latency and Bandwidth
3.4 Memory Hierarchy
3.4.1 Components of a Modern Memory Hierarchy
3.4.2 Temporal and Spatial Locality
3.4.3 Caching and Cache Memories
3.4.4 Main Memory
3.5 Virtual Memory Systems
3.5.1 Demand Paging
3.5.2 Memory Protection
3.5.3 Page Table Architectures
3.6 Memory Hierarchy Implementation
3.7 Input/Output Systems
3.7.1 Types of I/O Devices
3.7.2 Computer System Busses
3.7.3 Communication with I/O Devices
3.7.4 Interaction of I/O Devices and Memory Hierarchy
3.8 Summary
Superscalar Organization
4.1 Limitations of Scalar Pipelines
4.1.1 Upper Bound on Scalar Pipeline Throughput
4.1.2 Inefficient Unification into a Single Pipeline
4.1.3 Performance Lost Due to a Rigid Pipeline
4.2 From Scalar to Superscalar Pipelines
4.2.1 Parallel Pipelines
4.2.2 Diversified Pipelines
4.2.3 Dynamic Pipelines
4.3 Superscalar Pipeline Overview
4.3.1 Instruction Fetching
4.3.2 Instruction Decoding
4.3.3 Instruction Dispatching
4.3.4 Instruction Execution
4.3.5 Instruction Completion and Retiring
4.4 Summary
5 Superscalar Techniques
5.1 Instruction Flow Techniques
5.1.1 Program Control Flow and Control Dependences
5.1.2 Performance Degradation Due to Branches
5.1.3 Branch Prediction Techniques
5.1.4 Branch Misprediction Recovery
5.1.5 Advanced Branch Prediction Techniques
5.1.6 Other Instruction Flow Techniques
5.2 Register Data Flow Techniques
5.2.1 Register Reuse and False Data Dependences
5.2.2 Register Renaming Techniques
5.2.3 True Data Dependences and the Data Flow Limit
……
6 The PowerPc 620
7 Intel's P6 Microarchitecture
8 Survey of Superscalar Processors
9 Advanced Instruction Flow Techniques
10 Advanced Register Data Flow Techniques
11 Executing Multiple Threads
Index
鄂公网安备 42010302001612号 