VHDL与数字电路设计

Chapter 1　Developing Digital System
1.1　Digital Systems and Analog Systems
1.2　Two Methods of Digital Circuit Design
1.2.1　Traditional Method——Using Standard Logic Devices
1.2.2　Modern Method——Using Programmable Logic Devices
1.3　Introduction of Programmable Logic Devices
1.3.1　Early Programmable Logic Devices
1.3.2　Todays Programmable Logic Devices
1.4　Computer-aided Design of Logic Circuits on PLD
1.5　Digital Circuit Design Hierarchy
1.5.1　The System and Register Levels
1.5.2　The Gate Level
1.5.3　Transistor and Physical Design Levels
1.5.4　Top-down Modular Design
1.6　Design of PLD
1.6.1　The Design Cycle
1.6.2　Digital Circuit Modeling
1.6.3　Design Synthesis and Capture Tools
1.6.4　Logic Simulation
1.6.5　Libraries and 1P Core
PROBLEMS
Chapter 2　Programmable Logic Devices
2.1　Semicustom Logic Devices
2.2　Programmable Logic Arrays
2.2.1　Two-level AND-OR Arrays
2.2.2　PLA Circuit Structures
2.2.3　Realizing Logic Functions with PLAs
2.2.4　Output Polarity Options
2.3　Programmable Array Logic
2.3.1　PAL Circuit Structures
2.3.2　Realizing Logic Functions with PALs
2.3.3　Bidirectional Pins and Feedback Lines
2.3.4　Programmable Logic Macrocells
2.4　Complex Programmable Logic Devices （CPLDs）
2.5　Field-Programmable Gate Arrays
2.5.1　Programmable Gate Arrays
2.5.2　Logic Cell Arrays
2.5.3　Interconnections
PROBLEMS
Chapter 3　VHDL——A Programming Language
3.1　VHDL Design Entity
3.1.1　Entity Declaration
3.1.2　Architecture
3.2　Package
3.3　Using Subcircuits
3.4　Data Objects
3.4.1　Data Object Names
3.4.2　Data Object Values and Numbers
3.5　Signal Data Objects
3.5.1　BIT and BIT_VECTOR Types
3.5.2　STD_LOGIC and STD_LOGIC_VECTOR Types
3.5.3　SIGNED and UNSIGNED Types
3.5.4　INTEGER Type
3.5.5　BOOLEAN Type
3.6　CONSTANT and VARIABLE Data Objects
3.6.1　CONSTANT Type
3.6.2　VARIABLE Type
3.7　Type Conversion
3.8　Operators
3.9　Concurrent Assignment Statements
3.9.1　Simple Signal Assignment
3.9.2　Selected Signal Assignment
3.9.3　Conditional Signal Assignment
3.10　Sequential Assignment Statements
3.10.1　IF Statement
3.10.2　CASE Statement
3.10.3　LOOP Statements
3.10.4　PROCESS Statement
3.10.5　Statement Ordering
3.10.6　Using a VARIABLE in a Process
3.11　Three Other Statements
3.11.1　GENERATE Statement
3.11.2　Defining an Entity with GENERICs
3.11.3　Using Subcircuits with GENERIC Parameters
PROBLEMS
Chapter 4　Using VHDL for Describing Logic Circuits
4.1　Describing Combinational Circuits
4.1.1　VHDL Code of Multiplexer
4.1.2　VHDL Code of Decoder
4.1.3　VHDL Code of Encoder
4.1.4　VHDL Code of Comparator
4.1.5　VHDL Code of an Arithmetic Logic Unit
4.2　Designing Sequential Circuits
4.2.1　Implied Memory
4.2.2　VHDL of Latches
4.2.3　VHDL Code of Flip-Flops
4.2.4　VHDL Code of Registers
4.2.5　VHDL Code of Counters
4.3　State-Machine Design for VHDL
4.3.1　Introduction
4.3.2　Basic HDL Coding
4.3.3　State Assignment
4.3.4　Coding State Transitions
PROBLEMS
Chapter 5　VHDL Design Using Quartus Ⅱ
5.1　Typical CAD Flow
5.2　Getting Started
5.3　Starting a New Project
5.4　Design Entry Using VHDL Code
5.4.1　Using the Quartus I1 Text Editor
5.4.2　Using VHDL Templates
5.4.3　Adding Design Files to a Project
5.5　Compiling the Designed Circuit
5.6　Pin Assignment
5.7　Simulating the Designed Circuit
5.7.1　Creating the Waveforms
5.7.2　Performing the Simulation
5.7.3　Functional Simulation
5.7.4　Timing Simulation
5.8　Programming and Configuring the CPLD Device
5.9　Testing the Designed Circuit
PROBLEMS
Chapter 6　Experiments
6.1　Designing a Counting Clock
6.1.1　Functions
6.1.2　Preparations
6.1.3　Module Specification and Pin Signal Definitions
6.1.4　VHDL Source Codes
6.2　Designing a Digital Frequency Meter
6.2.1　Functions Requirements
6.2.2　Preparations
6.2.3　VHDL Source Codes
6.3　Designing an A/D Sampling Controller
6.3.1　Functions Requirements
6.3.2　Preparations
6.3.3　VHDL Source Codes
Glossary
References
Appendix　Internet Web Sites