Chapter 0 Reader’s Guide
0.1 Outline of the Book
0.2 A Roadmap for Reade and I tructo
0.3 Why Study Computer Organization and Architecture
0.4 Internet and Web ResourcesPART ONE OVERVIEW
Chapter 1 Introduction
1.1 Organization and Architecture
1.2 Structure and Function
1.3 Key Terms and Review Questio
Chapter 2 Computer Evolution and Performance
2.1 A Brief History of Compute
2.2 Designing for Performance
2.3 The Evolution of the Intel x86 Architecture
2.4 Embedded Systems and the ARM
2.5 Performance Assessment
2.6 Recommended Reading and Web Sites
2.7 Key Terms, Review Questio , and ProblemsPART TWO THE COMPUTER SYSTEM
Chapter 3 A TopLevel View of Computer Function andInterconnection
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
3.5 PCI
3.6 Recommended Reading and Web Sites
3.7 Key Terms, Review Questio , and Problems
Appendix 3A Timing Diagrams
Chapter 4 Cache Memory
4.1 Computer Memory System Overview
4.2 Cache Memory Principles
4.3 Elements of Cache Design
4.4 Pentium 4 Cache Organization
4.5 ARM Cache Organization
4.6 Recommended Reading
4.7 Key Terms, Review Questio , and Problems
Appendix 4A Performance Characteristics of TwoLevel Memories
Chapter 5 Internal Memory Technology
5.1 Semiconductor Main Memory
5.2 Error Correction
5.3 Advanced DRAM Organization
5.4 Recommended Reading and Web Sites
5.5 Key Terms, Review Questio , and Problems
Chapter 6 External Memory
6.1 Magnetic Disk
6.2 RAID
6.3 Optical Memory
6.4 Magnetic Tape
6.5 Recommended Reading and Web Sites
6.6 Key Terms, Review Questio , and Problems
Chapter 7 Input/Output
7.1 External Devices
7.2 I/O Modules
7.3 Programmed I/O
7.4 InterruptDriven I/O
7.5 Direct Memory Access
7.6 I/O Channels and Processo
7.7 The External Interface: FireWire and Infiniband
7.8 Recommended Reading and Web Sites
7.9 Key Terms, Review Questio , and Problems
Chapter 8 Operating System Support
8.1 Operating System Overview
8.2 Scheduling
8.3 Memory Management
8.4 Pentium Memory Management
8.5 ARM Memory Management
8.6 Recommended Reading and Web Sites
8.7 Key Terms, Review Questio , and ProblemsPART THREE THE CENTRAL PROCESSING UNIT
Chapter 9 Computer Arithmetic
9.1 The Arithmetic and Logic Unit (ALU)
9.2 Integer Representation
9.3 Integer Arithmetic
9.4 FloatingPoint Representation
9.5 FloatingPoint Arithmetic
9.6 Recommended Reading and Web Sites
9.7 Key Terms, Review Questio , and Problems
Chapter 10 I truction Sets: Characteristics and Functio
10.1 Machine I truction Characteristics
10.2 Types of Operands
10.3 Intel x86 and ARM Data Types
10.4 Types of Operatio
10.5 Intel x86 and ARM Operation Types
10.6 Recommended Reading
10.7 Key Terms, Review Questio , and Problems
Appendix 10A Stacks
Appendix 10B Little, Big, and BiEndian
Chapter 11 I truction Sets: Addressing Modes and Formats
11.1 Addressing
11.2 x86 and ARM Addressing Modes
11.3 I truction Formats
11.4 x86 and ARM I truction Formats
11.5 Assembly Language
11.6 Recommended Reading
11.7 Key Terms, Review Questio , and Problems
Chapter 12 Processor Structure and Function
12.1 Processor Organization
12.2 Register Organization
12.3 The I truction Cycle
12.4 I truction Pipelining
12.5 The x86 Processor Family
12.6 The ARM Processor
12.7 Recommended Reading
12.8 Key Terms, Review Questio , and Problems
Chapter 13 Reduced I truction Set Compute (RISCs)
13.1 I truction Execution Characteristics
13.2 The Use of a Large Register File
13.3 CompilerBased Register Optimization
13.4 Reduced I truction Set Architecture
13.5 RISC Pipelining
13.6 MIPS R4000
13.7 SPARC
13.8 The RISC ve us CISC Controve y
13.9 Recommended Reading
13.10 Key Terms, Review Questio , and Problems
Chapter 14 I tructionLevel Parallelism and Supe calarProcesso
14.1 Overview
14.2 Design Issues
14.3 Pentium 4
14.4 ARM CortexA8
14.5 Recommended Reading
14.6 Key Terms, Review Questio , and ProblemsPART FOUR THE CONTROL UNIT
Chapter 15 Control Unit Operation
15.1 Microoperatio
15.2 Control of the Processor
15.3 Hardwired Implementation
15.4 Recommended Reading
15.5 Key Terms, Review Questio , and Problems
Chapter 16 Microprogrammed Control
16.1 Basic Concepts
16.2 Microi truction Sequencing
16.3 Microi truction Execution
16.4 TI 8800
16.5 Recommended Reading
16.6 Key Terms, Review Questio , and Problems
PART FIVE PARALLEL ORGANIZATION
Chapter 17 Parallel Processing
17.1 The Use of Multiple Processo
17.2 Symmetric Multiprocesso
17.3 Cache Coherence and the MESI Protocol
17.4 Multithreading and Chip Multiprocesso
17.5 Cluste
17.6 Nonuniform Memory Access Compute
17.7 Vector Computation
17.8 Recommended Reading and Web Sites
17.9 Key Terms, Review Questio , and Problems
Chapter 18 Multicore Compute
18.1 HardwarePerformance Issues
18.2 Software Performance Issues
18.3 Multicore Organization
18.4 Intel x86 Multicore Organization
18.5 ARM11 MPCore
18.6 Recommended Reading and Web Sites
18.7 Key Terms, Review Questio , and Problems
Appendix A Projects for Teaching Computer Organization
and Architecture
A.1 Interactive Simulatio
A.2 Research Projects
A.3 Simulation Projects
A.4 Assembly Language Projects
A.5 Reading/Report Assignments
A.6 Writing Assignments
A.7 Test Bank
Appendix B Assembly Language and Related Topics
B.1 Assembly Language
B.2 Assemble
B.3 Loading and Linking
B.4 Recommended Reading and Web Sites
B.5 Key Terms, Review Questio , and ProblemsONLINE CHAPTERS
Chapter 19 Number Systems
19.1 The Decimal System
19.2 The Binary System
19.3 Converting between Binary and Decimal
19.4 Hexadecimal Notation
19.5 Key Terms, Review Questio , and Problems
Chapter 20 Digital Logic
20.1 Boolean Algebra
20.2 Gates
20.3 Combinational Circuits
20.4 Sequential Circuits
20.5 Programmable Logic Devices
20.6 Recommended Reading and Web Site
20.7 Key Terms and Problems
Chapter 21 The IA64 Architecture
21.1 Motivation
21.2 General Organization
21.3 Predication, Speculation, and Software Pipelining
21.4 IA64 I truction Set Architecture
21.5 Itanium Organization
21.6 Recommended Reading and Web Sites
21.7 Key Terms, Review Questio , and ProblemsONLINE APPENDICES
Appendix C Hash Tables
Appendix D Victim Cache Strategies
D.1 Victim Cache
D.2 Selective Victim Cache
Appendix E Interleaved Memory
Appendix F International Reference Alphabet
Appendix G Virtual Memory Page Replacement Algorithms
Appendix H Recu ive Procedures
H.1 Recu ion
H.2 Activation Tree Representation
H.3 Stack Processing
H.4 Recu ion and Iteration
Appendix I Additional I truction Pipeline Topics
I.1 Pipeline Reservation Tables
I.2 Reorder Buffe
I.3 Scoreboarding
I.4 Tomasulo’s Algorithm
Appendix J Linear Tape Open Technology
Appendix K DDR SDRAM
Glossary
References
Index
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